A review on advances in design methodologies for integrated circuits
Qingye Wei
The University of Southampton
DOI: https://doi.org/10.59429/esta.v12i1.9683
Keywords: Integrated circuits; Layout planning; Meta-heuristic Algorithms
Abstract
The field of integrated circuit (IC) design has witnessed remarkable advancements driven by the need for higher performance, reduced chip size, and enhanced energy efficiency. This review explores state-ofthe-art methodologies in IC design, with a focus on layout optimization and the application of metaheuristic algorithms such as simulated annealing and genetic algorithms. It also examines novel representation techniques like sequence pair, B*-tree, and corneal block sequences that address layout complexity. Furthermore, the study proposes integrating machine learning, reinforcement learning, and predictive models to enhance the adaptability and efficiency of design processes. By offering a comprehensive overview and presenting forward-looking perspectives, this review aims to contribute to the development of next-generation ICs, addressing scalability challenges and ensuring improved performance for advanced electronic systems.
References
[1] Nayak P. A study of technology roadmap for application-specific integrated circuit[D]. Rice University, 2021.
[2] Shalf J. The future of computing beyond Moore’s Law[J]. Philosophical Transactions of the Royal Society A, 2020, 378(2166): 20190061.
[3] Leiserson C E, Thompson N C, Emer J S, et al. There’s plenty of room at the Top: What will drive computer performance after Moore’s law?[J]. Science, 2020, 368(6495): eaam9744.
[4] Burg D, Ausubel J H. Moore’s Law revisited through Intel chip density[J]. PloS one, 2021, 16(8): e0256245.
[5] Ding B, Zhang Z H, Gong L, et al. A novel thermal management scheme for 3D-IC chips with multicores and high power density[J]. Applied thermal engineering 2020, 168: 114832.
[6] Huang C Y, Dewey G, Mannebach E, et al. 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling[C]//2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020: 20.6. 1-20.6. 4.
[7] Kang K, Benini L, De Micheli G. Cost-effective design of mesh-of-tree interconnect for multicore clusters with 3-D stacked L2 scratchpad memory[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 23(9): 1828-1841.
[8] Ben Abdallah A, Ben Abdallah A. 3D integration technology for multicore systems on-chip[J]. Advanced Multicore Systems-On-Chip: Architecture, On-Chip Network, Design, 2017: 175-199.
[9] Hu X, Stow D, Xie Y. Die stacking is happening[J]. IEEE micro, 2018, 38(1): 22-28.
[10] Ghaderi Z, Alqahtani A, Bagherzadeh N. AROMa: aging-aware deadlock-free adaptive routing algorithm and online monitoring in 3D NoCs[J]. IEEE Transactions on Parallel and Distributed Systems, 2017, 29(4): 772-788.
[11] J. Cong, C. Liu, and G. Luo, “Quantitative studies of impact of 3D IC design on repeater usage,” in Proc. Int. VLSI/ULSI Multilevel Interconnection Conf., 2008, pp. 344–348.
[12] Kim D H, Athikulwongse K, Healy M B, et al. Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)[J]. IEEE Transactions on Computers, 2013, 64(1): 112 125.